The invention is directed to an improved approach for designing, analyzing, and manufacturing integrated circuits.
An integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a-silicon wafer. Many phases of physical design may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language. An EDA system typically receives the high level behavior descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction using a computer synthesis process. A netlist describes interconnections of nodes and components on the chip and includes information of circuit primitives such as transistors and diodes, their sizes and interconnections, for example.
An integrated circuit designer may use a set of layout EDA application programs to create a physical integrated circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes. Typically, geometric information about the placement of the nodes and components onto the chip is determined by a placement process and a routing process. The placement process is a process for placing electronic components or circuit blocks on the chip and the routing process is the process for creating interconnections between the blocks and components according to the specified netlist. After an integrated circuit designer has created the physical design of the circuit, the integrated circuit designer then verifies and optimizes the design using a set of EDA testing and analysis tools.
Based upon the layout, photomasks are created for lithographic manufacturing of the electronic product. A photomask, or more simply a “mask,” provides the master image of one layer of a given integrated chip's physical geometries. A typical photolithography system projects UV light energy on to and through the mask in order to transmit the mask pattern in reduced size to the wafer surface, where it interacts with a photosensitive coating on the wafer. Other processes may also be performed during to manufacture an integrated circuit. For example, etching, electroplated copper deposition (ECD), and chemical mechanical polishing (CMP) may be used to form interconnects for the IC.
Rapid developments in the technology and equipment used to manufacture semiconductor ICs have allowed electronics manufacturers to create smaller and more densely packed chips in which the IC components, such as wires, are located very close together. When electrical components are spaced close together, the electrical characteristics or operation of one component may affect the electrical characteristics or operation of its neighboring components. The reaction or noise that is triggered by this interference between components is called the “crosstalk” effect.
With shrinking process node sizes, the inherent effects of process variations are playing a larger factor in defining the behavior of a circuit, and in particular, the extent and effects of crosstalk on the behavior of the circuit. Process variations may arise during the process of manufacturing the IC that cause the as-manufactured product to have different characteristics or dimensions from the as-designed product. These variations are commonly caused by side-effects of the processing used to manufacture the IC. For example, optical effects of using lithographic manufacturing process may cause variations to exist in the manufactured device from the originally intended feature dimensions and geometries of the layout. Variations in feature density, widths, and heights may also occur during the CMP, etching, and plating processes.
The process of performing crosstalk analysis is very complex, and is made even more difficult because of the effects of process variations. However, in the UDSM era, it is an imperative part of the design flow that the designers adequately analyze their designs for crosstalk. This is because crosstalk can cause functional or timing failures of the chip, thus leading to significant loss of yield.
Because of the complexity for performing crosstalk analysis, analysis tools generally tend to err on the side of pessimism, on the theory that it is better for the tool to overestimate a noise, rather than take the risk of underestimating a potential point of failure. The trick then is to make sure that the pessimism in analysis is as small as possible.
One of the key methods used in noise analysis to reduce pessimism is the use of timing windows. The concept of timing windows is based upon the formation of windows in which all aggressors nets cannot typically attack (e.g., cause noise due to coupling) a victim net at the same time. Only those aggressor nets that have switching activities in the same window can potentially attack a victim at the same time. The effect of crosstalk on delay can only be seen when the victim is switching. This implies that there must be some sort of overlap between the victim and aggressor's, or set of aggressors', timing windows.
However, timing windows themselves are approximate constructs, since they do not have any equivalent analytical description as a bound-based definition. When used incorrectly, the timing windows can itself lead to excessive pessimism, or worse, optimism.
Therefore, it is clear that there is a need for an improved approach to perform crosstalk and timing analysis for an electronic design. According to some embodiments of the invention, first-order parameterized analysis modeling is used to overcome the shortcomings of the existing approaches, and factor in the effect of process variations within the definition of timing windows.
Other and additional objects, features, and advantages of the invention are described in the detailed description, figures, and claims.